/*
	Copyright 2025 fu, 312011150@qq.com
	
	Licensed under the Apache License, Version 2.0 (the "License");         
	you may not use this file except in compliance with the License.        
	You may obtain a copy of the License at                                 
                                                                         
     http://www.apache.org/licenses/LICENSE-2.0                          
                                                                         
 Unless required by applicable law or agreed to in writing, software    
 distributed under the License is distributed on an "AS IS" BASIS,       
 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 See the License for the specific language governing permissions and     
 limitations under the License.          
*/
`include "defines.v"

// 译码模块
// 纯组合逻辑电路
module id (
	input wire rst,
	
	// from if_id
	input wire[`InstBus] inst_i,											// 指令内容
	input wire[`InstAddrBus] inst_addr_i,									// 指令地址
	
	// from regs
	input wire[`RegBus] reg1_rdata_i,										// 通用寄存器1输入数据
	input wire[`RegBus] reg2_rdata_i,										// 通用寄存器2输入数据
	
	// from csr reg
	input wire[`RegBus] csr_rdata_i,										// CSR寄存器输入数据
	
	// from ex
	input wire ex_jump_flag_i,												// 跳转标志
	
	// to regs
	output reg[`RegAddrBus] reg1_raddr_o, 									// 读通用寄存器1地址
	output reg[`RegAddrBus] reg2_raddr_o,									// 读通用寄存器2地址
	
	// to csr regs
	output reg[`MemAddrBus] csr_raddr_o,									// 读CSR寄存器地址
	
	//	to ex
	output reg[`MemAddrBus] op1_o,
	output reg[`MemAddrBus] op2_o,
	output reg[`MemAddrBus] op1_jump_o,
	output reg[`MemAddrBus] op2_jump_o,
	output reg[`InstBus] inst_o,										 	// 指令内容
	output reg[`InstAddrBus] inst_addr_o,									// 指令地址
	output reg[`RegBus] reg1_rdata_o,										// 通用寄存器1数据
	output reg[`RegBus] reg2_rdata_o,										// 通用寄存器2数据
	output reg reg_we_o,													// 写通用寄存器标志
	output reg[`RegAddrBus] reg_waddr_o,									// 写通用寄存器地址
	output reg csr_we_o,													// 写CSR寄存器标志
	output reg[`RegBus] csr_rdata_o,										// CSR寄存器数据
);
	
	wire[6:0] opcode = inst_i[6:0];
	wire[2:0] funct3 = inst_i[14:12];
	wire[6:0] funct7 = inst_i[31:25];
	wire[4:0] rd = inst_i[11:7];
	wire[4:0] rs1 = inst_i[19:15];
	wire[4:0] rs2 = inst_i[24:20];
	
	always @ (*) begin
		inst_o = inst_i;
		inst_addr_o = inst_addr_i;
		reg1_rdata_o = reg1_rdata_i;
		reg2_rdata_o = reg2_rdata_i;
		csr_rdata_o = csr_rdata_i;
		csr_raddr_o = `ZeroWord;
		csr_waddr_o = `ZeroWord;
		csr_we_o = `WriteDisable;
		op1_o = `ZeroWord;
		op2_o = `ZeroWord;
		op1_jump_o = `ZeroWord;
		op2_jump_o = `ZeroWord;
		
		case (opcode)
			`INST_TYPE_I: begin
				case (funct3)
					`INST_ADDI, `INST_SLTI, `INST_SLTIU, `INST_XORI, `INST_ORI, `INST_ANDI, `INST_SLLI, `INST_SRI: begin
						reg_we_o = `WriteEnable;
						reg_waddr_o = rd;
						reg1_raddr_o = rs1;
						reg2_raddr_o = `ZeroReg;
						op1_o = reg1_rdata_i;
						op2_o = {{20{inst_i[31]}}, inst_i[31:20]};
					end
					default: begin
						reg_we_o = `WriteDisable;
						reg_waddr_o = `ZeroReg;
						reg1_raddr_o = `ZeroReg;
						reg2_raddr_o = `ZeroReg;
					end
				endcase
			end
			`INST_TYPE_R_M: begin
				if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin
					case (funct3)
						`INST_ADD_SUB, `INST_SLL, `INST_SLT, `INST_SLTU, `INST_XOR, `INST_SR, `INST_OR, `INST_AND: begin
							reg_we_o = `WriteEnable;
							reg_waddr_o = rd;
							reg1_raddr_o = rs1;
							reg2_raddr_o = rs2;
							op1_o = reg1_rdata_i;
							op2_o = reg2_rdata_i;
						end
						default: begin
							reg_we_o = `WriteDisable;
							reg_waddr_o = `ZeroReg;
							reg1_raddr_o = `ZeroReg;
							reg2_raddr_o = `ZeroReg;
						end
					endcase
				end else if (funct7 == 7'b0000001) begin
					case (funct3)
						`INST_MUL, `INST_MULHU, `INST_MULH, `INST_MULHSU: begin
							reg_we_o = `WriteEnable;
							reg_waddr_o = rd;
							reg1_raddr_o = rs1;
							reg1_raddr_o = rs2;
							op1_o = reg1_rdata_i;
							op2_o = reg2_rdata_i;
						end
						`INST_DIV, `INST_DIVU, `INST_REM, `INST_REMU: begin
						
						end
						default: begin
						
						end
					endcase
				end
			end
			`INST_TYPE_L: begin
			
			end
			`INST_TYPE_S: begin
			
			end
			`INST_TYPE_B: begin
			
			end
			`INST_JAL: begin
			
			end
			`INST_JALR: begin
			
			end
			`INST_LUI: begin
			
			end
			`INST_AUIPC: begin
			
			end
			`INST_NOP_OP: begin
			
			end
			`INST_FENCE: begin
			
			end
			`INST_CSR: begin
			end
			default: begin
			
			end
		endcase
	end
endmodule